The present invention is generally directed to a method for passivating the back channel regions in amorphous silicon field effect transistors (FETs), particularly those employed in matrix addressed liquid crystal displays. More particularly, the present invention is related to a treatment process for amorphous silicon FET devices which results in significantly reduced levels of transistor "OFF" current.
In matrix addressed liquid crystal displays (LCDs), it is known to employ field effect transistor devices at each picture element (pixel). For display applications, each pixel is approximately 100 microns square. In matrix addressed liquid crystal displays, each one of the pixel elements is turned on and off through the operation of an FET. Furthermore, the desirability of low temperature processing favors the utilization of FET devices comprising doped and undoped amorphous silicon. In operation, a selected FET or set of FETs is turned "ON" and charge is permitted to accumulate on an adjoining pixel electrode, which together with a ground plane electrode, acts very much like a capacitive storage device. The electric field between the pixel electrode and a transparent ground plane electrode preferentially affects liquid crystal material disposed between these electrodes in a manner which changes their optical properties and thereby provides a display function. For purposes of image display stability, it is desired that any current that flows during FET "OFF" conditions is minimal. Typically, the OFF current is required to be less than 50 picoamperes. Low OFF currents ensure that charge placed upon the pixel electrodes persists for a desirably long time without the need for immediate refreshing. During this time, other pixels in the display may be addressed.
Amorphous silicon FETs typically employed in matrix addressed liquid crystal displays employ a structure in which a portion of the amorphous silicon material is exposed through a metal contact layer. The amorphous silicon layer also includes an upper layer of doped amorphous silicon material, this latter layer being exposed through openings in a metal contact layer. The region at the bottom of this contact metal gap forms the channel region of the device. It is known to remove the doped amorphous silicon layer between the metal contacts by etching methods. Typically an N+ layer of amorphous silicon is removed by etching in a barrel plasma etcher using molybdenum source and drain contact metal patterns as a mask. After etching, it is necessary to protect the exposed silicon surface from environmental contamination. The present invention is directed to a method for providing a desired degree of protection. If this protection is not provided, a net positive charge state tends to be produced on the exposed silicon surface. This induces an electron channel in the near surface region. These electrons are mobile and produce conduction between the source and drain, resulting in so-called back channel leakage. This back channel leakage increases OFF current levels. Since low OFF currents are required for display and imaging applications, this is a significant problem in devices of this kind. While silicon nitride protective caps are often employed as a passivating material, subsequent to back channel etching, it has been found that such passivating means alone are much more susceptible to the production of back channel leakage than processing in accordance with the present invention.